1. Field of the Invention
The present invention relates to a memory-contained processor having memories and a processor formed on the same chip, and more particularly to a memory-contained processor containing a cache memory with superior area efficiency.
2. Description of the Background Art
Processors such as microprocessor units (MPUs) or central processing units (CPUs) have come to operate at higher speed, for example at 100 MHz, or 200 MHz. On the other hand, dynamic random access memories (DRAMs) used as main memories, though much improved, still operate slower than processors. Such a difference in the speed of operation causes the processor to wait until necessary data is available. In order to improve system performance so that high speed data processing is performed with the minimum wait time, a high speed memory called a cache memory is placed between the main memory and the processor. The cache memory stores data frequently accessed by the processor.
Since the processing proceeds according to a program, it is accompanied by localization of an access region. Therefore, when the cache memory stores data requested by the processor (cache hit), it is highly likely that this cache memory stores data which is continuously accessed. If this data requested by the processor exists in the cache memory, data transfer is always performed between the processor and the cache memory. It can reduce the wait time of the processor, resulting in high speed processing. The main memory DRAM is accessed only when the data requested by the processor does not exist in the cache memory (cache miss).
By storing an appropriate number of cache blocks (each of which serves as a unit of data transfer in cache miss) of an appropriate size in the cache memory, the cache hit rate can be increased, the wait time of the processor can be shortened, and the high speed data processing is possible.
The cache hit rate can be increased by enlarging a storage capacity of the cache memory. A static random access memory (SRAM) is usually used as such cache memory.
FIG. 17 shows an example of the SRAM cell structure. In FIG. 17, the SRAM cell SMC includes a load element Z1 connected between a power supply node VCC and an internal storage node NA, a load element Z2 connected between power supply node VCC and an internal storage node NB, an n channel MOS transistor (insulated-gate type field-effect transistor) T1 connected between internal storage node NA and a ground node GND and having its gate connected to internal storage node NB, an n channel MOS transistor T2 connected between internal storage node NB and ground node GND and having its gate connected to internal storage node NA, an n channel MOS transistor T3 being conducted in response to a signal potential on a word line WL to electrically connect internal storage node NA to a bit line BL, an n channel MOS transistor T4 being conducted in response to the signal potential on word line WL to electrically connect internal storage node NB to a bit line/BL.
A row of SRAM cells SMCs are connected to word line WL. Bit lines BL and/BL transmit complementary data signals and they are arranged in a pair. A column of memory cells are connected to this bit line pair BL and /BL.
Load elements Z1 and Z2 have a function of pulling up storage node NA or NB to the level of power supply voltage VCC (the node and the voltage supplied thereto are designated by the same character) according to stored information, and they are formed by thin-film transistors or resistance elements.
MOS transistors T1 and T2 constitute a flip-flop and hold signal potentials at internal storage nodes NA and NB. When the signal potential on word line WL rises to an H level, MOS transistors T3 and T4 are conducted, connecting internal storage nodes NA and NB to bit lines BL and /BL, respectively. In this state, data reading or writing for this SRAM cell SMC is performed.
As shown in FIG. 17, SRAM cell SMC includes four MOS transistors, that is, MOS transistors T1 and T2 for storing data and MOS transistors T3 and T4 for accessing this SRAM cell SMC. This SRAM has the advantage of operating at high speed due to the transmission of complementary data signals and the static operation. However, it is disadvantageous in that the occupied area by one-bit memory cell SMC is large. As a result, when a cache memory is structured by using this SRAM cell SMC, the area occupied by this cache memory increases with the increase in the storage capacity of this cache memory. Especially, it is a big obstacle to one-chip implementation of a processor and a memory, which is a current trend, and to size reduction of a system.
FIG. 18 shows a structure of a DRAM cell. In FIG. 18, two DRAM cells DMCa and DMCb are shown. DRAM cell DMCa is arranged corresponding to a crossing of a word line WLa and bit line BL. DRAM cell DMCb is arranged corresponding to a crossing of a word line WLb and bit line /BL. Each one of DRAM cells DMCa and DMCb includes a capacitor C for storing information and an n channel MOS transistor Q being conducted in response to a signal potential of corresponding word line WL (WLa or WLb) to electrically connect capacitor C to a corresponding bit line BL or/BL.
In this DRAM also, a row of DRAM cells are connected to word lines WLa and WLb, respectively, and a column of memory cells are connected to bit line pair BL and /BL. One electrode node of capacitor C of these DRAM cells DMCa and DMCb is supplied with a constant cell plate voltage VCP. DRAM cells DMCa and DMCb each store information according to the amount of charges accumulated in the other electrode of this capacitor C. In reading memory cell data, the memory cell data is read to one of bit lines BL and /BL, and the other bit line supplies a reference potential for this memory cell data.
Each one of DRAM cells DMCa and DMCb is constituted by one MOS transistor and one capacitor C as shown in FIG. 18. Therefore, it includes fewer transistors than SRAM cell SMC shown in FIG. 17, and occupies approximately one fourth the area of SRAM cell SMC. Thus, this DRAM can implement a memory of a large storage capacity in a limited area.
However, in the DRAM which operates dynamically, it is necessary to precharge each signal line to a prescribed potential, and it cannot operate at higher speed than SRAM. Therefore, if the DRAM is simply used as a cache memory, it is difficult to implement a high speed cache memory.